library ieee;
use ieee.std_logic_1164.all;

entity dmem_tb is
end dmem_tb;

architecture behav_tb of dmem_tb is
    component dmem is
        port(
        a, wd: in std_logic_vector(31 downto 0);
        clk, we, dump: in std_logic;
        rd: out std_logic_vector(31 downto 0)
        );
    end component;

    signal a_s, wd_s, rd_s: std_logic_vector(31 downto 0);
    signal clk_s, we_s, dump_s: std_logic;

begin
    DM0: dmem port map(a_s, wd_s, clk_s, we_s, dump_s, rd_s);

    process -- Clock signal
    begin
        clk_s <= '1';
        wait for 1 ns;
        clk_s <= '0';
        wait for 1 ns;
    end process;

    process -- Some test values
    begin
        we_s <= '1';
        a_s <= "00000000000000000000000000000000";
        wd_s <= x"FFFFAAAA";
        wait for 2 ns;
        assert rd_s = x"FFFFAAAA" report "Unexpected rd 1" severity error;

        a_s <= "00000000000000000000000000000100";
        wd_s <= x"AAAA0000";
        wait for 2 ns;
        assert rd_s = x"AAAA0000" report "Unexpected rd 2" severity error;

        we_s <= '0';
        wd_s <= x"0000FFFF";
        a_s <= "00000000000000000000000000000000";
        wait for 2 ns;
        assert rd_s = x"FFFFAAAA" report "Unexpected rd 3" severity error;

        we_s <= '1';
        wait for 2 ns;
        assert rd_s = x"0000FFFF" report "Unexpected rd 4" severity error;

        dump_s <= '1';
        wait;
    end process;
end behav_tb;
